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ADE7816
CLKIN AND CLKOUT
An external clock or parallel resonant crystal is required to
clock the ADE7816 . If an external clock source is being used,
it should be connected to the CLKIN pin. The required clock
frequency for specified operation is 16.384 MHz. Alternatively,
a parallel resonant AT-cut crystal can be connected across the
CLKIN and CLKOUT pins. The ADE7816 has no internal load
capacitance and, therefore, load capacitors based on the data
sheet of the crystal manufacturer should be added on each pin.
ANALOG INPUTS
Input Pins
The ADE7816 has seven analog inputs that form six current
channels and one voltage channel. Current Channel A, Current
Channel B, and Current Channel C each consist of a pair of dif-
ferential input pins: IAP and IAN, IBP and IBN, and ICP and ICN.
Data Sheet
PGA Gain
The ADE7816 has three internal PGA gain amplifiers that can
be used to amplify the input signals by ×2, ×4, ×8 or ×16. The
PGA gain stage is often required when using a current sensor
that produces a low output voltage, such as Rogowski coils.
PGA1 affects Current Channel A, Current Channel B, and
Current Channel C and is controlled by Bits[2:0] (PGA1) of
the gain register (Address 0xE60F). PGA2 affects the voltage
channel and is controlled by Bits[5:3] (PGA2) of the gain register.
PGA3 affects Current Channel D, Current Channel E, and
Current Channel F and is controlled by Bits[8:6] (PGA3) of
the gain register.
Table 9 lists details on how the PGA gain affects the full-scale
input voltage.
Table 9. PGA Gain
Current Channel D, Current Channel E, and Current Channel F
all share a common reference, IN, and, therefore, are single-ended.
For consistency, it is recommended that all six current inputs be
connected in a single-ended configuration (see Figure 26 and
Figure 27). The voltage channel is a fully differential input that
consists of a pair of inputs: VP and VN. The voltage channel is
typically connected in a single-ended configuration.
The maximum input voltage that should be applied to any input
Gain
1
2
4
8
16
Full-Scale
Single-Ended
Input (mV)
±500
±250
±125
±62.5
±31.25
Gain Register (Address 0xE60F)
PGA1[2:0] PGA2[5:3] PGA3[8:6]
000 000 000
001 001 001
010 010 010
011 011 011
100 100 100
channel is ±500 mV. The maximum common-mode signal that is
allowed on the inputs is ±25 mV. Figure 25 shows a schematic of
the inputs and their relation to the maximum common-mode
voltage.
Digital Integrator
The ADE7816 includes a digital integrator that must be enabled
when using a di/dt sensor such as a Rogowski coil. This integrator
is enabled by setting the INTEN bit (Bit 0) of the CONFIG register
V 1
DIFFERENTIAL INPUT
V 1 + V 2 = 500mV MAX PEAK
COMMON MODE
V CM = ±25mV MAX
(Address 0xE618) to 1. When using the digital integrator, the
DICOEFF register (Address 0x4388) should be written to
0xFFF8000. For more details on the theory behind the digital
+500mV
V 1
VP
integrator, refer to the AN-1137 Application Note.
V CM
–500mV
V CM
VN
Figure 25. Maximum Input Level
Rev. A | Page 18 of 48
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